This invention relates to a charge transfer device and, more particularly, to a charge transfer device which may be advantageously employed in a charge transfer stage inclusive of an output section of a CCD solid-state imaging device.
In general, a charge transfer device employed in a charge transfer stage including an output section of a CCD solid-state imaging device is made up of a charge transfer unit for sequentially transferring signal charges and a charge detection unit constituted by a floating diffusion amplifier or a floating gate amplifier.
Above all, the charge detection unit by the floating gate amplifier employs a floating gate for non-destructively detecting the size of a signal charge lump as an image charge. Besides, it can be easily increased in density, while it has a small parasitic capacity and high sensitivity and is susceptible to noise to a lesser extent.
Such conventional charge transfer device has a p-type silicon substrate, for example, not shown, on which are formed a charge transfer section 1 for sequentially transferring signal charges e and a charge detection section 2 for detecting signal charges e transferred on the charge transfer section 1, as shown in FIG. 1.
In FIG. 1, the signal transfer section 1 is of a two-phase drive transfer system in which the signal charges e are transferred using two-phase clock pulses P.sub.1, P.sub.2 oppositely phased relative to each other. A charge transfer channel, not shown, which is a transfer channel for the signal charges e, is formed on top of the surface of the above-mentioned p-type silicon substrate. On a region of the charge transfer channel, a large number of sets of transfer electrodes, each consisting of a transfer gate electrodes (TG electrodes) 3 and a storage gate electrode (SG electrode) 4, are arrayed for extending in pre-set directions.
The clock pulse P.sub.1 is supplied to an odd group of the TG electrodes 3a and the SG electrodes 4a via an input terminal .phi..sub.1, while the other clock pulse P.sub.2 is supplied to an even group of the TG electrodes 3b and the SG electrodes 4b via an input terminal .phi..sub.2, whereby the signal charges e are transferred by the two-phase driving system towards the charge detecting section 2.
The charge detecting section 2 is constituted by a floating gate amplifier for non-destructively detecting the signal charges e transferred from the charge transfer section 1. The floating gate amplifier is made up of a first output gate electrode (first OG electrode) 5, formed adjacent to the SG electrode 4b of the final stage of the charge transfer section 1, floating gate electrodes (FG electrodes) 6, pre-charge gate electrodes (PG electrodes) 7a, 7b, a second output gate electrode (second OG electrode) 8 and a drain region 9. Similarly to the transfer electrode of the charge transfer section 1, the PG electrodes 7a, 7b are constituted by two electrodes, and are designed so that a potential barrier below the PG electrode 7a adjacent to the FG electrode 6 is higher than the potential barrier below the other PG electrode wall 7a.
In order for the level of the potential barrier below the PG electrode 7a adjacent to the FG electrode 6 to be lower than that of the potential barrier below the other PG electrode 7b, a channel region 12 below the PG electrode 7a adjacent to the FG electrode 6 is designed as an N-type impurity diffusion region of low impurity concentration, while the channel region 13 below the other PG electrode 7b is designed as an N-type impurity diffusion region of high impurity concentration. This enables the potential of the channel region 12 and the potential of the channel region 13 to be shallower and deeper in the state of thermal equilibrium. That is, a potential having a step-like descending shape is formed in the charge transfer direction.
Direct current voltages Vog1, Vog2 are supplied via input terminals .+-..sub.3, .+-..sub.5 to the first OG electrode 5 and the second OG electrode 8, respectively, whereby fixed potential barriers are formed below the first OG electrode 5 and the second OG electrode 8, respectively. A control pulse Pg is supplied via an input terminal .phi..sub.4 to each of the PG electrodes 7a and 7b so that the potential below the PG electrodes 7a, 7b becomes higher, while the potential barrier below the PG electrode 7a becomes lower than the potential well below the PG electrode 6. At this time, the electrical charge is transferred to below the other PG electrode 7b over the potential barrier below the PG electrode 6.
When the control pulse Pg ceases to be supplied to the PG electrodes 7a, 7b, the potential below the PG electrodes 7a, 7b is lowered and an initial state is again reached, that is, the potential barrier below the PG electrode 7b becomes higher than the potential barrier below the neighboring second OG electrode 8. At this time, the signal charge e accumulated below the PG electrode 7b ia swept into a neighboring drain region 9 over the potential barrier below the second OG electrode 8, as shown.
A reset pulse Pr is supplied to the gate electrode of the FG electrode 6, the drain terminal of which is connected to the source of a switching transistor Tr, the drain terminal of which is fed with a power source voltage for resetting Vr. The potential below the FG electrode 6 is reset, that is fixed at a level corresponding to the source voltage Vr, by the aforementioned reset pulse Pr being fed to the gate electrode of the switching transistor Tr. An amplifier in, for example, a source follower configuration 10 is connected to the downstream side of the FG electrode 6. After the reset pulse Pr ceases to be supplied to the gate electrode of the switching transistor, voltage changes by the signal voltage e transferred to and accumulated below the FG electrode 6 are supplied to the amplifier 10 so as to be outputted as an output signal S at an output terminal .phi.out.
With the above-described charge transfer device, the signal charge e needs to be accumulated in a potential well below the FG electrode 6 and be swept into the drain region 9 via a region below the PG electrodes 7a, 7b and the second OG electrode after outputting of the output signal S. To this end, it becomes necessary for the potential barrier below the PG electrode 7a to be deeper than the potential well below the FG electrode 6.
However, since the source voltage for resetting Vr, supplied to the FG electrode 6, is of a larger magnitude, a still larger voltage is required in order to produce a potential deeper than the potential well below the PG electrode 6. On the other hand, with the conventional charge transfer device, a transfer channel 11 below the FG electrode 6 is an N-type impurity diffusion region of high impurity concentration, as indicated by N in FIG. 1, while a transfer channel 12 below the PG electrode 7a is an N-type impurity diffusion region of low impurity concentration, as indicated by N.sup.- in FIG. 1, so that a potential deeper than the potential well below the FG electrode 6 cannot be produced unless a still larger voltage is applied to a region below the PG electrode 7a.
Consequently, should the voltage to be supplied to the PG electrode 7a and the resetting source voltage to be applied to the FG electrode 6 be obtained from the same power source, a booster circuit needs to be interposed for boosting the voltage supplied to the PG electrode 7a.
The booster circuit is usually constituted by a charging pump which is in need of a wide capacity and area. This reads to an increased area set aside for the charge transfer channel 1 and a peripheral circuit, thus increasing the number of transfer stages in the charge transfer channel 1 and making it difficult to form the peripheral circuit on one and the same chip.
On the other hand, with the above-described conventional charge transfer device, the control pulse Pg having a pulse width T is delayed by time t for generating the reset pulse Pr to be supplied to the gate electrode of the switching transistor Tr for resetting the voltage level of the FG electrode 6, as shown in FIG. 2. Thus the voltage level below the FG electrode 6 is reset after lapse of the delay time t as from the time the control pulse Pg reaches a high level.
Meanwhile, the potential barrier formed below the PG electrodes 7a and 7b starts to be moved downward as from the time the control pulse has gone high in order to transfer the signal charge e accumulated in the potential well below the FG electrode 6 to below the PG electrode 7b during the time the control pulse Pg is at the high level. The effect of capacitive coupling due to parasitic capacitance between the FG electrode 6 and the PG electrode 9a becomes manifest during the delay time t which elapses since the control pulse Pg goes high until the reset pulse Pr goes high, as shown in FIG. 2, so that a noise N due to the potential shift is superimposed on the output signal S. Since such noise N incur serious deterioration in the playback picture quality, it becomes necessary to provide a noise suppressing circuit, thereby complicating the circuit construction.
Another conventional charge transfer device, shown in FIG. 3, has a p-type silicon substrate, for example, not shown, on which are formed a charge transfer section 31 for sequentially transferring signal charges e and a charge detection section 32 for detecting signal charges e transferred on the charge transfer section 31.
The signal transfer section 31 is of a two-phase drive transfer system in which the signal charges e are transferred using two-phase clock pulses P.sub.1, P.sub.2 oppositely phased relative to each other.
The charge detecting section 32 is constituted by a floating gate amplifier for non-destructively detecting signal charges transferred from the charge transfer section 31. The floating gate amplifier includes an output gate OG adjacent to the last stage of the charge transfer section 31, a floating gate FG, a discharging element 33, made up of a pre-charge gate PG and a drain region D, and a source follower circuit 34, made up of an output device Q1 and a load resistor device Q2, on the downstream side of the floating gate amplifier.
The output gate OG has its gate electrode fed with a dc voltage V.sub.og, while the precharge gate has its gate electrode supplied with a control pulse .phi..sub.pg. The signal charge transferred from the charge transfer section 31 via the output gate OG and accumulated in the floating gate FG is swept in this manner into the drain region D.
To the gate electrode of the floating gate FG is connected a switching transistor Tr fed with the reset pulse Pr and with a resetting source voltage Vr coupled to its drain terminal. The aforementioned reset pulse Pr is fed to the gate electrode of the switching transistor Tr for fixing the potential below the floating gate electrode at a Vr level. A voltage changes .DELTA.V is supplied to the downstream side source follower circuit 34 by the signal charges transferred to and accumulated below the floating gate electrode, and is outputted as an output voltage (image signal) S at an output terminal .phi..sub.0 of the source follower circuit 34.
However, with the above-described charge transfer device, since the voltage V.sub.og applied to the output gate OG is a fixed voltage, the parasitic capacitance between the floating gate FG and the output gate OG acts as hindrance to improvement in the charge-voltage conversion efficiency.